The present disclosure relates to Synchronous input/output (I/O) on a computer, and more specifically, to Synchronous input/output cache line padding.
Storage Area Networks (SANs), as described by the Storage Networking Industry Association (SNIA), are high performance networks that enable storage devices and computer systems to communicate with each other. In large enterprises, multiple computer systems or servers have access to multiple storage control units within the SAN. Typical connections between the servers and control units use technologies such as Ethernet or Fibre-Channel, with the associated switches, I/O adapters, device drivers and multiple layers of a protocol stack. Fibre-channel, for example, as defined by the International Committee for Information Technology Standards (INCITS) T11 Committee, defines physical and link layers FC0, FC1, FC2 and FC-4 transport layers such as the Fibre Channel Protocol (FCP) for small computer system interface (SCSI) and FC-SB-3 for Fibre Connectivity (FICON).
Synchronous I/O causes a software thread to be blocked while waiting for the I/O to complete, but avoids context switches and interrupts. This works well when the I/O is locally attached with minimal access latency, but as access times increase, the non-productive processor overhead of waiting for the I/O to complete becomes unacceptable for large multi-processing servers. This disclosure describes an interface with sufficiently low latency that synchronous access is viable even for large multi-processing servers. Some network topologies may implement Synchronous I/O using a PCI Express (PCIe) link as defined by the Peripheral Component Interconnect (PCI)-Special Interest Group (SIG). In PCIe architecture, all memory write operations are considered ‘Posted’ type commands. Posted type commands in PCIe do not expect a response or acknowledgment for the write transaction. For data integrity in storage systems, it is important that data is never lost and the system maintains its integrity. To ensure data integrity of write operations in Synchronous I/O, the system requires an acknowledgment that the write data has been successfully written in the storage control unit.
Different processor architectures support different cache line sizes (e.g., 64, 128 bytes, etc.). When writing data that is less than the cache line size, the full cache line must be fetched and then the modified data must be merged with the original data into a unified cache line. In other words writing a partial cache line forces a read-modify-write operation. Synchronous I/O systems may perform status transfers for write acknowledgments that are less than a typical cache line size (e.g., 8 bytes) in comparison to the available cache data size (e.g., 64, 128 bytes, etc.). These partial write operations can cause processing inefficiency and latency.